Currently, only a dual gate is available at the 14 nm technology node. The dual gate includes a single gate (SG) (logic) operating at a high voltage (V), e.g., Vmax of 0.945 V, and an extended gate (EG) input/output (I/O) operating at a voltage (VDD) of 1.2 V for a gate channel with a length of 100 nm. The existing 14 nm technology cannot meet consumer demands for higher VDD application because a SG with higher VDD runs a risk of time dependent dielectric breakdown (TDDB) or bias temperature instability (BTI) margin. In addition, an EG with higher VDD application has a lower speed due to a thick gate dielectric thickness (TOX).
Current 14 nm technology does not offer a triple gate due to process challenges. The process challenges for forming a triple gate in a 14 nm technology are illustrated in FIGS. 1 through 3. Adverting to FIG. 1, an EG 101, a MG 103 and a SG 105 are formed in a silicon (Si) substrate 107. An interfacial layer (IL) 109 is conformally formed over the Si substrate 107. As illustrated in FIG. 2, a photoresist 201 is formed over the IL 109 over the EG 101. Then, the IL 109 over the MG 103 and SG 105 are etched, thereby forming IL 109′. The photoresist 201 is then stripped (not shown for illustrative convenience) followed by a clean process, e.g., standard clean 1 (SC1). Next, the IL 109′ over the MG 103 is oxidized (not shown for illustrative convenience). The process steps in FIG. 3 are similar to the process steps of FIG. 2. Adverting to FIG. 3, a photoresist 301 is formed over the ILs 109 and 109′ over the EG 101 and MG 103. Then, the IL 109′ over the SG 105 is etched, thereby forming IL 109″. The photoresist 301 is then stripped (not shown for illustrative convenience) followed by SC1. Next, the IL 109″ over SG 105 is oxidized (not shown for illustrative convenience). These multiple process steps of lithography, etching and oxidation to form a triple gate adds to process complexity.
A need therefore exists for methodology enabling a middle gate (MG) in the dual gate process for forming a triple gate with simpler process steps.